Title :
Incremental netlist compilation for IKOS hardware logic simulator
Author :
Wang, Kai ; Chen, Jerry
Author_Institution :
IKOS Syst. Inc., Sunnyvale, CA, USA
Abstract :
Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be reproduced and can be loaded to the simulator for the times of occurrences by adjusting for the base offsets
Keywords :
circuit analysis computing; logic CAD; IKOS hardware logic simulator; hierarchical network patterns; Artificial intelligence; Data structures; Hardware; Joining processes; Logic design; Partitioning algorithms; Pins; Signal design; Signal resolution;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1989.123223
