Ground bounce in CMOS ASICs

Author

Steele, David P.

Author_Institution

NCR Corp., Colorado Springs, CO, USA

fYear

1989

fDate

25-28 Sep 1989

Lastpage

38078

Abstract

A study has been undertaken to investigate the ground bounce phenomena in CMOS ASICs (application-specific integrated circuits). A simple mathematical analysis was performed to help gain an intuitive understanding of the problem. SPICE simulations were then performed to build a more detailed model. The SPICE model allowed different problem solving approaches to be compared in a straightforward manner. Laboratory experiments were performed to confirm the validity of the simulation and mathematical analyses. The results indicate that there are effective measures which can be taken to reduce the magnitude of voltage transients induced by the device and to minimize the device´s sensitivity to ground bounce

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit analysis computing; integrated logic circuits; CMOS ASICs; SPICE model; SPICE simulations; application-specific integrated circuits; ground bounce phenomena; logic ICs; mathematical analysis; voltage transients reduction; Analytical models; Application specific integrated circuits; Circuit simulation; Laboratories; Mathematical analysis; Performance gain; Problem-solving; SPICE; Semiconductor device modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123224

Filename

123224