• DocumentCode
    2083722
  • Title

    A circuit simulation model of submicron MOSFETs for SPICE

  • Author

    Chung, Steve S. ; Lin, T.S. ; Chen, Y.G.

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    1989
  • fDate
    25-28 Sep 1989
  • Lastpage
    38108
  • Abstract
    A computationally efficient submicron MOSFET I-V model for circuit simulation in SPICE is provided. It is an improved model of the LEVEL3 MOS model in SPICE and supports the design of conventional as well as LDD (lightly doped drain) MOSFETs down to the submicron range. The drain-source series resistance and three-dimensional geometry effects are included in the model. In addition, the model allows fast extraction of model parameters which can be linked with SPICE. Accuracy and benchmark tests show substantial improvements over the original LEVEL3 model
  • Keywords
    MOS integrated circuits; circuit analysis computing; insulated gate field effect transistors; semiconductor device models; I-V model; LDD devices; LEVEL3 MOS model; SPICE; circuit simulation model; computationally efficient; drain-source series resistance; lightly doped drain; submicron MOSFETs; three-dimensional geometry effects; Circuit simulation; Circuit testing; Geometry; MOSFETs; SPICE; Semiconductor device modeling; Silicon; Solid modeling; Threshold voltage; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
  • Conference_Location
    Rochester, NY
  • Type

    conf

  • DOI
    10.1109/ASIC.1989.123225
  • Filename
    123225
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2083722