DocumentCode
2084040
Title
Architecture of reprogrammable processor specified for video processing
Author
Szymanski, T. ; Kielbik, R. ; Napieralski, Andrzej
Author_Institution
Dept. of Microelectron. & Comput. Sci., Tech. Univ. Lodz, Poland
fYear
2001
fDate
12-17 Feb. 2001
Firstpage
47
Lastpage
48
Abstract
In this paper a reprogrammable video processor architecture is presented. The processor is based on FPGA technology so it can be programmed to work with different algorithms prepared by the user (i.e. edge detection). Processing performance can be very high since each algorithm definition is hardware optimized.
Keywords
digital signal processing chips; field programmable gate arrays; real-time systems; reconfigurable architectures; video signal processing; FPGA technology; image processing; real-time motion processing; reprogrammable processor architecture; video processor architecture; Computer science; Field programmable gate arrays; Frequency synchronization; Hardware; Image edge detection; Image processing; Integrated circuit reliability; Microelectronics; Operating systems; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
CAD Systems in Microelectronics, 2001. CADSM 2001. Proceedings of the 6th International Conference. The Experience of Designing and Application of
Conference_Location
Lviv-Slavsko, Ukraine
Print_ISBN
966-553-079-8
Type
conf
DOI
10.1109/CADSM.2001.975730
Filename
975730
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