Current-mode logic techniques for CMOS mixed-mode ASICs

Current-steering logic (CSL) has been developed especially for high-precision, high-speed, mixed-mode application-specific integrated circuits (ASICs). Using simple CMOS circuitry reminiscent of bipolar integrated injection logic, the logic levels of a CSL gate are realized in the current domain by steering a constant DC bias current. Internal voltage swings are typically less than one volt. Consequently, measured power supply (V_dd) current spikes are typically only 15 μA for a CSL inverter implemented in a 2-μm p-well CMOS technology, a reduction of two orders of magnitude compared to the 1.5-mA current spikes typical of a conventional static CMOS inverter. The reduction in digital switching noise allows the development of higher performance on-chip analog circuitry in CMOS mixed-mode applications minimum measured propagation delay is about 500 ps with a power-delay product of 0.35 pJ