Title :
A 5GHz CMOS PLL with low KVCO and extended fine-tuning range
Author :
Bruss, Stephen P. ; Spencer, Richard R.
Author_Institution :
Solid-State Circuits Res. Lab., Univ. of California, Davis, CA
fDate :
June 17 2008-April 17 2008
Abstract :
A 5 GHz dual-path integer-N PLL uses an LC VCO and softly switched capacitors in the integral path to extend the fine-tuning range while keeping KVCO low. The loop BW is 80 kHz, the reference spur level is Lt -70 dBc with a 1MHz reference frequency and total loop filter capacitance of 31 pF. The measured phase noise is Lt -78 dBc/Hz and -115 dBc/Hz at 10 kHz and 1MHz offsets, respectively. This 0.23 mm2 PLL is fabricated in a 90 nm standard digital CMOS process and consumes 10 mW from a 1.2 V supply.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; phase noise; voltage-controlled oscillators; CMOS PLL; LC VCO; digital CMOS process; dual-path integer-N PLL; extended fine-tuning range; frequency 5 GHz; phase noise; softly switched capacitors; CMOS process; Capacitance; Capacitors; Filters; Frequency locked loops; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Voltage-controlled oscillators; CMOS; Integer-N; KVCO; PLL; Phase locked loop; VCO; dual-path; loop filter; reference spur; soft switching; softly switched; spur; voltage controlled oscillator;
Conference_Titel :
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-1808-4
Electronic_ISBN :
1529-2517
DOI :
10.1109/RFIC.2008.4561526
