Test generation for digital device on FPGA, CPLD

Author

Shkil, Alexander ; Skvortsova, Olga ; Mehedy, Masud MD ; Jahirul, H.H.M.

Author_Institution

Computer-aided Design Dept., Kharkov Tech. Univ. of Radioelectronics, Ukraine

fYear

2001

fDate

12-17 Feb. 2001

Firstpage

83

Lastpage

84

Abstract

The algorithm of test generation based on faults lists cubic cover (FLCC) and single logical path sensitization is offered. The realization of the algorithm is oriented to Field Programable Gate Arrays (FPGAs) up to 200000 gates, including more than 20 types of trigger structures. The projects language description - VHDL, supports the design systems of corporations Aldec and Xilinx.

Keywords

automatic test pattern generation; field programmable gate arrays; integrated circuit testing; logic testing; programmable logic devices; CPLD; FPGA; VHDL; faults lists cubic cover; single logical path sensitization; test generation algorithm; Circuit faults; Circuit testing; Design automation; Design engineering; Equations; Fault detection; Field programmable gate arrays; Logic testing; Programmable logic arrays; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

CAD Systems in Microelectronics, 2001. CADSM 2001. Proceedings of the 6th International Conference. The Experience of Designing and Application of

Conference_Location

Lviv-Slavsko, Ukraine

Print_ISBN

966-553-079-8

Type

conf

DOI

10.1109/CADSM.2001.975752

Filename

975752