Title :
A 64 bit CMOS mainframe execution unit macrocell with error detecting circuit
Author :
Hayashi, Teruaki ; Doi, Toshio ; Yamagishi, Mikio ; Koide, Kazuo ; Ishiyama, Akira ; Hiramatsu, Masataka ; Yamagiwa, Akira
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 64-bit CMOS mainframe execution unit macrocell with error detecting circuits is proposed. It adopts a parity predicting logic structure in order to reduce the number of circuit stages in the ALU (arithmetic and logic unit) critical path. By utilizing this structure, a one-bit-error detecting function is integrated. A novel CMOS precharged circuit is also developed to shorten the time required to precharge the whole circuit. Through the use of these techniques, 30% faster operation is achieved
Keywords :
CMOS integrated circuits; error detection; mainframes; microprocessor chips; 64 bit; CMOS; arithmetic and logic unit; error detecting circuit; mainframe execution unit macrocell; one-bit-error detecting function; operating speed; parity predicting logic structure; precharged circuit; Application specific integrated circuits; CMOS logic circuits; Delay effects; Hardware; Logic circuits; Macrocell networks; Signal detection;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164088
