DocumentCode :
2084417
Title :
Scalable parametrizable SMP system core architecture
Author :
Melnyk, Anatoly ; Dunets, Bohdan
Author_Institution :
Dept. of Comput. Eng., Lviv Polytech. Nat. Univ., Lvov, Ukraine
fYear :
2001
fDate :
12-17 Feb. 2001
Firstpage :
90
Lastpage :
91
Abstract :
The levels of scalability and architecture of scalable parametrizable shared memory symmetric multiprocessor (SMP) system core are considered. Proposed scalable parametrizable SMP system architecture is intended for creation ASIC optimised for source algorithm. Based on proposed architecture high-level ASIC synthesis tools are presented. The proposed high-level synthesis tools allow to create custom ASIC which bases on programming language algorithm description.
Keywords :
application specific integrated circuits; high level synthesis; parallel architectures; shared memory systems; ASIC; high-level synthesis; scalable parametrizable SMP system core architecture; shared memory symmetric multiprocessor; source programming language algorithm; Algorithm design and analysis; Application specific integrated circuits; Computer languages; Design engineering; Electronic design automation and methodology; Geometry; High level synthesis; Integrated circuit modeling; Scalability; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
CAD Systems in Microelectronics, 2001. CADSM 2001. Proceedings of the 6th International Conference. The Experience of Designing and Application of
Conference_Location :
Lviv-Slavsko, Ukraine
Print_ISBN :
966-553-079-8
Type :
conf
DOI :
10.1109/CADSM.2001.975755
Filename :
975755
Link To Document :
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