Title :
The DT-model: high-level synthesis using data transfers
Author :
Tarafdar, Shantanu ; Leeser, Miriam
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
We present a new model for formulating the classic HLS subproblems: scheduling, allocation, and binding. The model is unique in its use of data-transfers as the basic entity in synthesis. A data transfer represents the movement of one instance of data and contains the operation sourcing the data and all the operations using it. Our model compels the storage architecture of the design to be optimized concurrently with the execution unit. We have built a high-level synthesis system, Midas, based on our data transfer model. Midas generates designs with smaller storage and data transfer requirements than other HLS systems.
Keywords :
application specific integrated circuits; high level synthesis; DT-model; Midas; allocation; binding; data transfers; high-level synthesis; scheduling; Application specific integrated circuits; Bandwidth; Broadcasting; Data mining; Design optimization; High level synthesis; Integrated circuit synthesis; Multimedia systems; Permission; Processor scheduling;
Conference_Titel :
Design Automation Conference, 1998. Proceedings
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-89791-964-5