Automating the calculation of 3D interconnect parasitics

A comparison of planar and conformal 3D circuit descriptions has shown that as circuit complexity increases, so too does the percentage increase in interconnect capacitance found using conformal data compared with interconnect capacitance found using planar data. Software has been described which automatically generates a conformal 3D representation of an IC. An example of how the conformal 3D data might be used has been described, showing that parasitic interconnect capacitances can have an appreciable effect on circuit operation. The 3DTOP software has been shown to be successful in representing IC topography. Further work is being done to achieve a more realistic topographical description