High-speed implementation of Smith-Waterman algorithm for DNA sequence scanning in VLSI

In this paper, a novel pipelined algorithm is applied in the hardware implementation of Smith-Waterman algorithm. The proposed algorithm can cut down the computation time from O(m+n) to O(m+n/J), where J is the pipeline level, m and n are the lengths of the query sequence and subject sequence respectively. It´s obvious that if the length of subject sequence is much larger than the query sequence, i.e., n>>m, the computation of scanning protein sequences will be speeded up by a factor of J.