DocumentCode
2084787
Title
Fast Path Performance of Packet Cache Router Using Multi-core Network Processor
Author
Yamamoto, Shu ; Nakao, Akihiro
Author_Institution
Nat. Inst. of Inf. & Commun. Technol., Tokyo, Japan
fYear
2011
fDate
3-4 Oct. 2011
Firstpage
89
Lastpage
90
Abstract
The packet cache router enabling the packet-level redundant data elimination is effective to reduce the P2P swarm traffic traversing ISP inter-domain links. To deploy the packet cache router in the ISP networks, the high performance packet processing is required. In this paper, we implement a packet cache router by a multi-core network processor using fast path/slow path application structure and evaluate its performance.
Keywords
cache storage; memory architecture; multiprocessing systems; peer-to-peer computing; redundancy; ISP interdomain link; ISP network; P2P swarm traffic; fast path application; high performance packet processing; multicore network processor; packet cache router; packet-level redundant data elimination; slow path application; Communication systems; Educational institutions; Synchronization; Throughput; P2P; fast path; packet cache router; performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Architectures for Networking and Communications Systems (ANCS), 2011 Seventh ACM/IEEE Symposium on
Conference_Location
Brooklyn, NY
Print_ISBN
978-1-4577-1454-2
Electronic_ISBN
978-0-7695-4521-9
Type
conf
DOI
10.1109/ANCS.2011.22
Filename
6062718
Link To Document