OASYS: a framework for analog circuit synthesis

Author

Harjani, Ramesh

Author_Institution

Mentor Graphics Corp., San Jose, CA, USA

fYear

1989

fDate

25-28 Sep 1989

Lastpage

37987

Abstract

A description is given of a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks, each with associated design knowledge. The author also describes mechanisms for selecting from among alternate design styles and translating performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. The role such a synthesis system can play in exploring the space of designable circuits is examined

Keywords

application specific integrated circuits; circuit CAD; knowledge based systems; linear integrated circuits; ASIC design; CAD; CMOS operational amplifiers; OASYS; abstract functional blocks; analog circuit synthesis; comparators; computer aided design; design knowledge; hierarchical structure; knowledge-based synthesis tool; performance specification translation; process parameters; sized transistor schematics; Analog circuits; Application specific integrated circuits; CMOS process; Circuit synthesis; Circuit topology; Design automation; Graphics; Operational amplifiers; Prototypes; Space exploration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123242

Filename

123242