DocumentCode
2084896
Title
On memory allocation for high-speed packet analysis applications
Author
Bonelli, Nicola ; Gazzarrini, Loris ; Giordano, Stefano ; Procissi, Gregorio ; Trammell, Brian
Author_Institution
CNIT at Univ. di Pisa, Pisa, Italy
fYear
2013
fDate
9-13 June 2013
Firstpage
3814
Lastpage
3818
Abstract
The evolution of commodity hardware makes it a very attractive platform to develop high-performance networking applications that are affordable to deploy. All but the most trivial applications must copy packets into user-space for further analysis. Therefore, the allocation of memory for these copies becomes a performance-critical operation. In this work, we present a multi-layer slice memory allocator specifically designed to take advantage of spatial and temporal locality in dealing with high-speed packet processing applications. Experimental results show that the proposed approach clearly outperforms existing memory allocators in common networking use-cases.
Keywords
multi-threading; packet switching; resource allocation; storage management; high speed packet processing application; high-performance networking application; multilayer slice memory allocation; multithreaded networking application; spatial locality; temporal locality; Context; Hardware; IP networks; Instruction sets; Kernel; Resource management;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications (ICC), 2013 IEEE International Conference on
Conference_Location
Budapest
ISSN
1550-3607
Type
conf
DOI
10.1109/ICC.2013.6655150
Filename
6655150
Link To Document