DocumentCode
2084965
Title
Performance enhancement in disturbance rejection by PID controller in series with low pass filter
Author
Patil, S.S. ; Malwatkar, G.M. ; Kulkarni, J.V.
Author_Institution
Dept. of Instrum. & Control, Vishwakarma Inst. of Technol., Pune, India
fYear
2012
fDate
18-20 Dec. 2012
Firstpage
1
Lastpage
5
Abstract
In this paper a new tuning procedure is described for the ideal PID controller in series with the first-order low pass filter. It is based on the direct synthesis approach. Analytical expressions for the PID controller are derived for a common type of process model. Although the controller is designed for disturbance rejection, the set point response is satisfactory and can be improved by adjusting a single set point weighing factor b. Three simulation examples demonstrate that the proposed design method results in very good control for process models. IAE (Internal absolute error) of the proposed method is having smaller value than DS-d controller. In example 2 it is reduced up to 85%. As a result the proposed design method provides better disturbance rejection than the standard direct synthesis.
Keywords
closed loop systems; control system synthesis; low-pass filters; performance index; stability; three-term control; transfer functions; tuning; DS-d controller; IAE; PID controller; closed loop transfer function; controller design; direct synthesis approach; disturbance rejection; first-order low pass filter; internal absolute error; performance enhancement; process model; set point response; single set point weighing factor; tuning procedure; Direct Synthesis; Disturbance rejection; Integral absolute error; Low pass filter; PID controller;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Intelligence & Computing Research (ICCIC), 2012 IEEE International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4673-1342-1
Type
conf
DOI
10.1109/ICCIC.2012.6510263
Filename
6510263
Link To Document