Title :
FPGA implementation of parallel digital image processor
Author :
Brylski, Przemyslaw ; Strzelecki, Michal
Author_Institution :
Inst. of Electron., Tech. Univ. of Lodz, Lodz, Poland
Abstract :
This paper describes a FPGA implementation of the parallel digital image processor for an image segmentation and other analysis like edge detection or noise removal. The architecture and algorithm modifications presented in this paper are aimed to reduction the FPGA resources, namely the area of the image pixel that represents basic image processing unit.
Keywords :
edge detection; field programmable gate arrays; image denoising; image segmentation; FPGA implementation; edge detection; image processing unit; image segmentation; noise removal; parallel digital image processor; Field programmable gate arrays; Hardware; Image segmentation; Microcontrollers; Read only memory; Registers; Synchronization;
Conference_Titel :
Signal Processing Algorithms, Architectures, Arrangements, and Applications Conference Proceedings (SPA), 2010
Conference_Location :
Poznan
Print_ISBN :
978-1-4577-1485-6
Electronic_ISBN :
978-83-62065-07-3
