High performance on the fly reconfigurable MIMO detector

Upcoming wireless communication standards such as 802.11 n, WiMax etc require support for multiple modulation schemes. These standards all have multiple transmit and receive antennas(MIMO). Hence, the MIMO detector hardware should be able to accommodate different modulation schemes preferably on a single reconfigurable architecture. This paper presents an high performance FPGA implementation of a novel MIMO detector architecture that is able to reconfigure on the fly and provides quasi-optimal Bit Error Rate(BER). The design is implemented in Xilinx Virtex-4, and achieves a sustained throughput of 1.72 Gbps for QPSK, 860 Mbps for 16-QAM, and 430 Mbps for 64-QAM. The total area is approximately 140.26 KGates equivalent.