Dynamically regularized RLS-DCD algorithm and its FPGA implementation

In this paper, we present an FPGA implementation of a dynamically regularized recursive least squares adaptive filtering algorithm based on dichotomous coordinate descent iterations. The algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. The proposed implementation allows significant increase in the weight update rate compared to a implementation based on unregularized QR decomposition; for 16 and 64-element adaptive antenna arrays, the update rate is as high as 176 kHz and 31 kHz, respectively.