DocumentCode
2086596
Title
Architecture-aware design of a decimation filter based on a dual wordlength multiply-accumulate unit
Author
Lindahl, Erik ; Gustafsson, Oscar
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Linkoping
fYear
2008
fDate
26-29 Oct. 2008
Firstpage
1897
Lastpage
1901
Abstract
In this work we present the design and implementation of a decimation filter for an audio range DeltaSigma-modulator. The architecture is based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input. Each stage is composed of FIR filters which are mapped to the MAC unit. The design trade-offs and decisions for co-design of architecture and filters are discussed.
Keywords
FIR filters; delta-sigma modulation; FIR filters; architecture-aware design; audio range DeltaSigma-modulator; decimation filter; dual wordlength multiply-accumulate unit; Bandwidth; Filtering; Finite impulse response filter; Frequency conversion; IIR filters; Noise figure; Noise shaping; Quantization; Sampling methods; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2008 42nd Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
978-1-4244-2940-0
Electronic_ISBN
1058-6393
Type
conf
DOI
10.1109/ACSSC.2008.5074758
Filename
5074758
Link To Document