DocumentCode
2087257
Title
PROOFS: a super fast fault simulator for sequential circuits
Author
Cheng, Wu-tung ; Patel, Janak H.
Author_Institution
AT&T Bell Labs., Princeton, NJ, USA
fYear
1990
fDate
12-15 Mar 1990
Firstpage
475
Lastpage
479
Abstract
This paper describes PROOFS, a super fast fault simulator for synchronous sequential logic circuits. PROOFS achieves high performance by combining all the advantages in differential fault simulation, single fault propagation, and parallel fault simulation to minimize the memory requirements, to reduce events that need to be simulated, and to simplify the complexity of the software implementation. The experimental results of PROOFS and other available fault simulators on 20 benchmark circuits showed that PROOFS is the best
Keywords
fault location; logic CAD; logic testing; sequential circuits; PROOFS; complexity; differential fault simulation; logic circuits; parallel fault simulation; sequential circuits; single fault propagation; software implementation; super fast fault simulator; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Discrete event simulation; Fault detection; Logic testing; Sequential circuits; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location
Glasgow
Print_ISBN
0-8186-2024-2
Type
conf
DOI
10.1109/EDAC.1990.136694
Filename
136694
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