Title :
A 0.5 μm BiCMOS SOG with selectable 5 V/3.3 V operations
Author :
Tanaka, Yasunori ; Sei, Toshikazu ; Ishimoto, Shinji ; Ishibashi, Masahiro ; Kurahara, Akiro ; Kobayashi, Teruo
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A 0.5-μm BiCMOS SOG (sea-of-gates) with selectable 5-V/3.3-V operations is described. On-chip voltage converters for power distribution and selectable 5-V/3.3-V level interface circuits are proposed and successfully applied to a BiCMOS SOG with an optimized array architecture. High-speed, low-power, and high-reliability operations are demonstrated with a 0.5-μm BiCMOS process and 3.3-V operation
Keywords :
BIMOS integrated circuits; VLSI; logic arrays; power supply circuits; 0.5 micron; 3.3 V; 3.3-V operation; 5 V; BiCMOS SOG; gate arrays; high-reliability operations; level interface circuits; on-chip voltage convertors; optimized array architecture; power distribution; sea-of-gates; selectable 5 V/3.3 V operations; BiCMOS integrated circuits; Bipolar transistor circuits; Circuit simulation; Energy consumption; MOS devices; Power generation; Power supplies; Switches; Variable structure systems; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164099
