High level test generation using data flow descriptions

To significantly expedite the test generation process for sequential VLSI circuits, the hierarchy in the circuit descriptions should be exploited. Conventional test generators can provide tests for relatively small modules, which are typically embedded in large circuits. This paper considers test generation for complex VLSI circuits composed of many interconnected modules. In contrast to the previous approaches, the authors use high-level primitives and data flow descriptions to perform hierarchical test generation. Data flow descriptions provide the set of valid control signals to be activated for a particular data path to be active. Sequential propagation and justification of signals is carried out recursively. Results are presented based on an implementation of the algorithm in LISP on a Texas Instruments Explorer