Tree-Based Partitioning Approach for Network-on-Chip Synthesis

Since most System-on-Chips (SoCs) consist of heterogeneous IP core(s), application-specific Network on Chip (NoC) architectures are appropriate to meet the design requirements. The energy and performance optimization in the NoC design will continue to be the main design goal in nanoscale technologies. In this paper, we present a new hierarchal partitioning approach considering not only the reduction of wire length among cores, but also the optimization of switching power consumption subject to performance constraints. The experimental results on different benchmarks showed that our NoC topology synthesis algorithm can effectively save power and improve performance.