Delay-sensitive power management for packet switches

Power management has become a critical issue for communication and computing infrastructures. In this paper, we develop systematic and heuristic algorithms for managing communication switches with multiple speed (throughput) modes. Switch speed is increased by activating additional network processor cores, voltage/frequency scaling of the electronics, etc. Higher speed modes burn more power. The developed power (speed) control algorithms are responsive to switch queue backlogs and aim to efficiently trade backlog vs. power costs, so as to minimize the long-run overall backlog and power cost. We first systematically model the system in a Dynamic Programming (DP) framework, where the optimal control can be computed in principle. Unfortunately, the complexity is so high that even for a 2 × 2 switch the computation time is practically infeasible. We therefore develop an Approximate Dynamic Programming (ADP) algorithm based on the Q-learning framework, which has good computation and performance properties. We also develop two low-complexity heuristic power controls, one based on a “myopic” view of the control problem, and the other on “congestion-awareness” of the standard maximum weight matching scheme. We study the performance of the Q-learning and heuristic controls against the optimal one (which we can practically compute only for the 2×2 switch case), and coPmment on their efficiency. We also extend the method and results to the general case of multiprocessor computing resources.