Title :
FPGA implementaion of FEC for 10G-EPON
Author :
Xicong Li ; Yinying Cao ; Xue Chen ; Weidong Gao
Author_Institution :
State Key Lab. of Inf. Photonics & Opt. Commun. (BUPT), Beijing, China
Abstract :
New parallel RS(255,223) encoder and decoder architectures for 10G EPON FEC are presented and realized in FPGA. The proposed architectures can operate at 156.25MHz to achieve the throughput of 10.3125Gbps with small hardware-complexity and low latency.
Keywords :
codecs; field programmable gate arrays; forward error correction; logic design; optical fibre LAN; 10G EPON FEC; FPGA implementaion; bit rate 10.3125 Gbit/s; decoder architectures; frequency 156.25 MHz; hardware-complexity; parallel RS(255,223) encoder;
Conference_Titel :
Communications and Photonics Conference (ACP), 2012 Asia
Conference_Location :
Guangzhou
Print_ISBN :
978-1-4673-6274-0
