FPGA implementation of QR decomposition for MIMO-OFDM using four CORDIC cores

A low-resource implementation of QR decomposition (QRD) is proposed for MIMO-OFDM systems that employ turbo MMSE-IC (Minimum mean square error interference cancellation) detector. The proposed implementation uses only four CORDIC cores for QR decomposition of complex-valued matrices while existing systolic array architecture requires 15 to 38 CORDIC cores to achieve similar throughput. For 4-by-4 MIMO with 1024 subcarrier OFDM, the turbo MMSE-IC requires 1024 QRD of 4-by-4 complex matrices followed by back substitution. Each matrix QRD is accompanied by rotations of four vectors for the second and subsequent turbo iterations. The proposed architecture implements the multiple vector rotation by multipliers rather than CORDIC cores, thus saving resources. When combined with a 2-dimensional array of back substitution, the proposed QRD architecture can achieve 64-matrix pipelining and a throughput of seven clocks per matrix for MMSE-IC calculation. The proposed MMSE-IC architecture has been implemented in Altera Stratix IV FPGA with LDPC decoding and other baseband receiver components.