DocumentCode
2088736
Title
A 0.8-μm BiCMOS sea-of-gates implementation of the tandem banyan fast packet switch
Author
Chiussi, Fabio M. ; Amano, Hideharu ; Tobagi, Fouad A.
Author_Institution
Dept. of Electr. Eng., Stanford Univ., CA, USA
fYear
1991
fDate
12-15 May 1991
Abstract
A simple, high-performance architecture for fast packet switching, called the tandem banyan switching fabric, has been proposed. The authors report on the implementation of the routing functionality of this architecture, augmented with self-testing and fault-recovery capabilities, using a high-performance BiCMOS sea-of-gates on a 0.8-μm technology
Keywords
BIMOS integrated circuits; automatic testing; logic arrays; packet switching; semiconductor switches; switching systems; 0.8 micron; BiCMOS; fault-recovery capabilities; high-performance architecture; routing functionality; sea-of-gates; self-testing; tandem banyan fast packet switch; Asynchronous transfer mode; BiCMOS integrated circuits; Computer architecture; Computer simulation; Delay; Energy consumption; Fabrics; Packet switching; Switches; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.164104
Filename
164104
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