3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

Low-voltage high-machine-cycle BiCMOS circuit techniques for deep submicron BiCMOS RISC (reduced instruction set computer) processors are discussed. The feedback massive-input logic (FML) concept reduces by 3-4 times the number of transistors and the power within the framework of fully static logic. A quasi-complementary buffer circuit provides unprecedentedly excellent low-supply-voltage performance even below 3 V. Sequential circuits are enabled to operate at low voltages with good performance leverage over CMOS by the novel QC-BiCMOS flip-flop. It is demonstrated that the BiCMOS continues to have superior performance over CMOS in the sub-0.3-μm sub-3-V region, which promises 250-MHz-level parallel processing RISCs and ASICs (application-specific integrated circuits)