Design for manufacturing strategies to bring silicon process to 32nm node

The IC manufacturing industry has extended optical lithography way beyond what was originally conceivable since it is the most economical method for volume manufacturing. Using hyper NA (>1) and optimized illumination in combination with resolution enhancement technology (RET) mask is considered as the mainstream lithography to enable silicon process to 32 nm node. IC design and manufacturing sectors have communicated via design rules. Since 90 nm node, it is often insufficient only to spell out manufacturing specific constraints through conventional design rules. The use of RET masks for manufacturing have made it ever more challenging to communicate, and yet - a direct and comprehensive communication is necessary for assuring a reasonable device yield on wafers. Many DFM solution tools have been proposed but thus far none has addressed the need for a full information flow from manufacturing to IC design. In this report, we propose to use a universal process model file (PMF) as a means to communicate between manufacturing and design communities