Accurate modeling and simulation of bridging faults

A transistor-level examination of bridging faults and the resulting logic-level bridging fault model are described. Experiments with simulations and silicon demonstrate its accuracy. It is shown how to determine the logic value resulting from a bridging fault. This leads to a novel approach for test pattern generation and fault simulation. It is pointed out that the voting model accurately describes the behavior of shorted nodes in CMOS custom digital circuits. The logic value of shorted nodes is equal to the logic value output by the circuit with the most current drive. The threat of an intermediate voltage is very slight; therefore, bridging faults result in valid logic values on the shorted nodes