• DocumentCode
    2089555
  • Title

    The architecture of the GenTest sequential test generator

  • Author

    Bencivenga, Robert ; Chakraborty, Tapan J. ; Davidson, Scott

  • Author_Institution
    AT&T Bell Lab., Princeton, NJ, USA
  • fYear
    1991
  • fDate
    12-15 May 1991
  • Abstract
    GenTest is an automatic test pattern generator for sequential circuits. There are few constraints on the circuit, and scan design is not required. GenTest consists of the STG3 test generator and the DSIM differential fault simulator. The architecture of GenTest is described in detail, including the test generator, the embedded fault simulator, and the models of sequential elements used. GenTest has recently been extended to support test generation for circuits to be tested using current monitoring or IDDQ. Results of runs on the ISCAS´89 benchmarks are provided
  • Keywords
    automatic test equipment; logic testing; DSIM differential fault simulator; GenTest; STG3 test generator; architecture; automatic test pattern generator; benchmarks; current monitoring; current testing; embedded fault simulator; sequential circuits; sequential test generator; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Integrated circuit testing; Sequential analysis; Sequential circuits; System testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0015-7
  • Type

    conf

  • DOI
    10.1109/CICC.1991.164113
  • Filename
    164113
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2089555