DocumentCode :
2089601
Title :
Automatic generation of timing specifications for CMOS transistor subnetworks
Author :
Tjärnström, Robert
Author_Institution :
Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden
fYear :
1990
fDate :
12-15 Mar 1990
Firstpage :
524
Lastpage :
528
Abstract :
A method for automatic and hierarchical generation of timing specifications for CMOS transistor subnetworks is presented. The result is delays and timing constraints relating the pins of the cells, which then can be handled at the gate/latch level. It can be used for verification, performance estimation and as timing data for cell libraries and multilevel simulators. The approach is fast since it is static and only the unique cell types need to be analysed. When used for verification by comparison this provides an important complement to functional verifiers
Keywords :
CMOS integrated circuits; circuit analysis computing; formal specification; CMOS transistor subnetworks; automatic generation; cell libraries; delays; multilevel simulators; performance estimation; timing constraints; timing data; timing specifications; Added delay; Automatic logic units; Circuits; Costs; Libraries; Physics; Pins; SPICE; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
Type :
conf
DOI :
10.1109/EDAC.1990.136702
Filename :
136702
Link To Document :
بازگشت