DocumentCode
2089738
Title
Evolvable hardware: from on-chip circuit synthesis to evolvable space systems
Author
Stoica, Adrian
Author_Institution
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
fYear
2000
fDate
2000
Firstpage
161
Lastpage
169
Abstract
Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments on selected applications, and presents a perspective on the development of the field. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. These characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life. Expanding reconfiguration to other types of spacecraft hardcore (i.e. optics, MEMS, etc.) could lead to evolvable space systems
Keywords
evolutionary computation; logic CAD; reconfigurable architectures; EHW; Evolvable Hardware; Field Programmable Transistor Array; automatic synthesis; evolvable space systems; fault-tolerance; fuzzy logics; on-chip circuit synthesis; reconfigurable hardware; Circuit faults; Circuit simulation; Circuit synthesis; Electronic circuits; Fault tolerance; Fuzzy logic; Genetics; Guidelines; Hardware; Space vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Conference_Location
Portland, OR
ISSN
0195-623X
Print_ISBN
0-7695-0692-5
Type
conf
DOI
10.1109/ISMVL.2000.848615
Filename
848615
Link To Document