High accuracy and high speed testing method for wafer level reliability

Author

Iwai, Kazuo ; Endo, Mamoru ; Saito, Yukiya. ; Ito, Taro ; Kasai, Atsushi ; Saito, Yuji. ; Mori, Katsumi ; Namose, Isamu

Author_Institution

Seiko Epson Corp., Nagano, Japan

fYear

2005

fDate

13-15 Sept. 2005

Firstpage

151

Lastpage

154

Abstract

The ephemeralization of LSI products urges the acceleration of development and the faster products release. In order to shorten the product launching process, the new wafer level reliability TEG and the quicker and easier testing methods were developed and introduced. Consequently, this has led to the reinforcement of the quality analysis and the brushing up its quality level in the earlier stage of development, and resulted in reducing the product launching time by 67%.

Keywords

integrated circuit manufacture; integrated circuit reliability; integrated circuit testing; large scale integration; product development; quality management; LSI products; high accuracy testing method; high speed testing method; large scale integration; product launching process; quality analysis; test element group; wafer level reliability; Guidelines; Indium tin oxide; Insulation testing; Large scale integration; Life estimation; MOSFETs; Manufacturing processes; Mass production; Plasma measurements; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on

Print_ISBN

0-7803-9143-8

Type

conf

DOI

10.1109/ISSM.2005.1513321

Filename

1513321