BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest

Hash functions form an important category of cryptography, which is widely used in a great number of protocols and security mechanisms. SHA-2 is the up to date NIST standard, but is going to be substituted in the near future with a new, modern one. NIST has selected the Second Round Candidates of the SHA-3 Competition. A year is allocated for the public review of these algorithms, and the Second SHA-3 Candidate Conference is being planned for August 23-24, 2010, after Crypto 2010. This paper deals with FPGA implementations of BLAKE hash functions family, which is one of the finalists. In this work, a VLSI architecture for the BLAKE family is proposed. For every hash function of BLAKE (-28, -32, -48, & -64), a hardware implementation is presented. The introduced integrations are examined and compared with hardware implementation terms. Computational efficiency of SHA-3 finalists in silicon, is one of the evaluation criteria of SHA-3.