Title :
Implementation of multiple-valued multiplier on GF(3m) using current mode CMOS
Author :
Seong, Hyeon Kyeong ; Choi, Jai Seok ; Shin, Boo Sik ; Kim, Heung Soo
Author_Institution :
Dept. of Comput. Sci. & Eng., Sangji Univ., South Korea
Abstract :
The multiplication algorithm of two polynomials on finite fields GF(3m) is presented. The 3-valued multiplier of the serial-in/parallel-out modular structures on GF(33) to be performed on the presented multiplication algorithm is implemented by current-mode CMOS. The current-mode CMOS 3-valued multiplier is implemented two GF(3) multipliers and two GF(3) adders. Performances of the proposed circuits are evaluated using Pspice simulations with 2.0 μm standard CMOS device parameters, 20 μA unit current level and 3.3 V VDD voltage supply
Keywords :
CMOS logic circuits; Galois fields; adders; current-mode logic; digital arithmetic; multiplying circuits; multivalued logic; multivalued logic circuits; 2 mum; 20 muA; 3-valued multiplier; 3.3 V; CMOS device parameters; GF(3) adders; GF(3) multipliers; GF(3m); Pspice simulations; current level; current mode CMOS; current-mode CMOS 3-valued multiplier; finite fields; multiple-valued multiplier; multiplication algorithm; polynomials; serial-in/parallel-out modular structures; Adders; Circuit simulation; Galois fields; Performance evaluation; Polynomials; Voltage;
Conference_Titel :
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Conference_Location :
Portland, OR
Print_ISBN :
0-7695-0692-5
DOI :
10.1109/ISMVL.2000.848623
