A planarized multilevel interconnect scheme with embedded low-dielectric-constant polymers for sub-quarter-micron applications

Author

Shin-Puu Jeng ; Mi-Chang Chang ; Kroger, T. ; McAnally, P. ; Havemann, R.H.

Author_Institution

Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1994

fDate

7-9 June 1994

Firstpage

73

Lastpage

74

Abstract

The new embedded polymer structure combines the advantages of SiO/sub 2/ and low dielectric constant of polymeric materials. The interconnect performance is improved through line-to-line capacitance reduction by utilizing polymer only between tightly spaced lines. Double-level-metal interconnect structures have been successfully fabricated using a variety of low-dielectric-constant insulators. The new multilevel interconnect scheme alleviates many of the integration and reliability problems associated with polymers, and can be easily adopted to standard production process.<>

Keywords

VLSI; circuit reliability; dielectric thin films; integrated circuit technology; metallisation; permittivity; polymer films; 0.3 micron; dielectric constant; double-level-metal interconnect structures; embedded low-dielectric-constant polymers; interconnect performance; line-to-line capacitance reduction; planarized multilevel interconnect scheme; reliability; standard production process; sub-quarter-micron applications; tightly spaced lines; Capacitance; Conducting materials; Crosstalk; Dielectric constant; Dielectric materials; Dielectrics and electrical insulation; Etching; Polymers; Thermal conductivity; Thermal stability;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324371

Filename

324371