DocumentCode
2090048
Title
Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars
Author
Ghavami, B. ; Tajary, A. ; Raji, M. ; Pedram, H.
Author_Institution
Comput. Eng. & Inf. Technol. Dept., Amirkabir Univ. of Technol., Tehran, Iran
fYear
2010
fDate
5-7 July 2010
Firstpage
173
Lastpage
178
Abstract
High defect density and extreme process variation for nanoscale self-assembled crossbar-based architectures have been expected to be as fundamental design challenges. Consequently, defect and variation issues must be considered on logic mapping on nanoscale crossbars. In this paper, we investigate a greedy algorithm for the variation and defect aware logic mapping of crossbar arrays. Based on Mont-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as variation unaware and exhaustive search mapping in terms of accuracy as well as runtime.
Keywords
Monte Carlo methods; greedy algorithms; logic circuits; logic design; reconfigurable architectures; Mont-Carlo simulation; crossbar arrays; defect aware logic mapping; design mapping; greedy algorithm; reconfigurable nanoscale crossbars; Bipartite graph; Delay; Logic functions; Nanoscale devices; Nanotubes; Nanowires; Wires; Logic Mapping; Nano Crossbar; defect; variation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location
Lixouri, Kefalonia
Print_ISBN
978-1-4244-7321-2
Type
conf
DOI
10.1109/ISVLSI.2010.43
Filename
5572766
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