A fast IP-core integration methodology for SoC design

Author

Filho, J.Ad.´O. ; De Lima, Manoel Eusébio ; Maciel, Paulo Romero ; Moura, Juliana ; Celso, Bruno

Author_Institution

Centre for Informatics, Univ. Fed. de Pernambuco, Brazil

fYear

2003

fDate

8-11 Sept. 2003

Firstpage

131

Lastpage

136

Abstract

The system on a chip (SoC) has become a reality, hosting the design of complex circuits into a single programmable device, supporting different cores for microprocessors, interfaces, buses, etc. However, the automatic inclusion of new general cores, from different providers, via a standard bus still needs a reliable interface mechanism to guarantee the correct protocol conversion and performance. This work presents a CAD tool to cope with this problem, based on a Petri net protocol conversion approach in a high level behavioral specification, focusing on bus planning and core integration.

Keywords

Petri nets; hardware description languages; industrial property; integrated circuit design; logic CAD; protocols; system buses; system-on-chip; CoreBond CAD tool; IP-core integration methodology; IP-core reuse; Petri net protocol conversion; SoC design; VHDL; bus planning; core integration; high level behavioral specification; interfaces; microprocessors; system on a chip; Design automation; Design methodology; Informatics; Integrated circuit reliability; Integrated circuit synthesis; Microprocessors; Petri nets; Protocols; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on

Print_ISBN

0-7695-2009-X

Type

conf

DOI

10.1109/SBCCI.2003.1232818

Filename

1232818