Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell

Author

Nishihara, T. ; Moriya, H. ; Ikeda, N. ; Aozasa, H. ; Miyazawa, Y.

Author_Institution

ULSI Res. & Dev. Lab., Sony Corp., Kanagawa, Japan

fYear

1994

fDate

7-9 June 1994

Firstpage

39

Lastpage

40

Abstract

Data retention in DRAM cells with ultra-thin bonded SOI film is investigated using 256 kbit fully functional test chip of 0.4 /spl mu/m design rule. In order to minimize an accumulation of minority carriers in channel region, we adopt a PMOS cell transistor. As a result, a retention time of 47 seconds for 50% bit fail at 25/spl deg/C, which is determined by a subthreshold diffusion current in the cell transistor, is obtained. A possibility of further improvement in retention time is then discussed. An importance of an elimination of GIDL is also pointed out.<>

Keywords

DRAM chips; MOS integrated circuits; cellular arrays; integrated circuit testing; minority carriers; semiconductor-insulator boundaries; silicon; 25 degC; 256 Kbit; 47 s; GIDL; PMOS cell transistor; buried capacitor cell; channel region; data retention; design rule; fully functional test chip; minority carriers; subthreshold diffusion current; ultra-thin-film-SOI DRAM; Binary search trees; Bipolar transistors; Bonding; Capacitance; Capacitors; Laboratories; Random access memory; Surface topography; Temperature; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324388

Filename

324388