A hardware multi-threading architecture for protocol processors

Multi-task is an important feature of network protocols, which encourages various hardware multi-threading architectures for network processors. In this paper, we proposed a pipelined multi-threading solution which is able to convert an existing single-threading processor into multi-threading one. This solution is independent on the original architecture and only involves division of pipeline stages, integration of thread context and stall control logics. A prototype of a 4-threaded processor was implemented and functionally verified in a MAC protocol application. Moreover, we also estimated its active power consumption and circuit area with 45 nm cell library, and our result shows that our solution saves 20.0% area than multi-core architecture while consuming similar power and performing same throughput.