Title :
BLAS Comparison on FPGA, CPU and GPU
Author :
Kestur, Srinidhi ; Davis, John D. ; Williams, Oliver
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
High Performance Computing (HPC) or scientific codes are being executed across a wide variety of computing platforms from embedded processors to massively parallel GPUs. We present a comparison of the Basic Linear Algebra Subroutines (BLAS) using double-precision floating point on an FPGA, CPU and GPU. On the CPU and GPU, we utilize standard libraries on state-of-the-art devices. On the FPGA, we have developed parameterized modular implementations for the dot-product and Gaxpy or matrix-vector multiplication. In order to obtain optimal performance for any aspect ratio of the matrices, we have designed a high-throughput accumulator to perform an efficient reduction of floating point values. To support scalability to large data-sets, we target the BEE3 FPGA platform. We use performance and energy efficiency as metrics to compare the different platforms. Results show that FPGAs offer comparable performance as well as 2.7 to 293 times better energy efficiency for the test cases that we implemented on all three platforms.
Keywords :
field programmable gate arrays; matrix multiplication; CPU; FPGA optimizations; basic linear algebra subroutines; dot-product multiplication; double-precision floating point; embedded processors; energy efficiency; floating point values; high performance computing; massively parallel GPU; matrix-vector multiplication; parameterized modular implementations; scientific codes; Adders; Field programmable gate arrays; Graphics processing unit; Kernel; Libraries; Pipelines; Random access memory;
Conference_Titel :
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location :
Lixouri, Kefalonia
Print_ISBN :
978-1-4244-7321-2
DOI :
10.1109/ISVLSI.2010.84