Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits

Author

Burnett, D. ; Erington, K. ; Subramanian, C. ; Baker, K.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1994

fDate

7-9 June 1994

Firstpage

15

Lastpage

16

Abstract

As the number of transistors integrated on a circuit continues to increase, roughly doubling every 18 months, the impact of transistor variations on circuit performance becomes more significant. Even in the absence of systematic variations (implant nonuniformities, Leff and Weff variations), there exists a fundamental variability in the threshold voltage V/sub T/ due to the finite number of dopant atoms in the extremely small MOSFET channel area. This work presents for the first time the impact of these fundamental V/sub T/ variations on SRAM cell stability and CMOS logic performance. We also analyze the impact of device scaling on these V/sub T/ variations and propose guidelines for future SRAM cell design.<>

Keywords

CMOS integrated circuits; SRAM chips; insulated gate field effect transistors; integrated logic circuits; 0.5 micron; CMOS logic performance; MOSFET channel area; SRAM cell design; SRAM cell stability; circuit performance; device scaling; dopant atoms; high-density SRAM; high-density logic circuits; static RAM; threshold voltage variations; transistor variations; CMOS logic circuits; Circuit optimization; Guidelines; Implants; Logic circuits; Logic devices; MOSFET circuits; Random access memory; Stability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324400

Filename

324400