A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network

With the increasing number of processor cores in chip multi-processors (CMPs), 2D Mesh has been gaining wide acceptance for inter-core on-chip communication. Program performance is more sensitive to the router latency than to the link bandwidth. This paper presents a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output queues scheme. The router delay model of DVOQR is derived based on the logical effect theory, and validated against Synopsys PrimeTime in TSMC 65nm technology. Results show that the critical path delay of the flit switch stage is more sensitive to the depth of unified dynamic buffer than to the link bandwidth. The critical path delay of DVOQR increases FO4 when the depth of Unified Dynamic Buffer (UDB) doubled. The frequency of DVOQR can reach 2.5GHz, which is improved by 20% compared to the virtual channel router, while the router only takes up 0.404mm².