Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology

Network-on-chip (NoC) architectures have been recently proposed as the communication framework for large-scale chips. The design of the routing system for the packet-switched on-chip network is one of the critical issues for the success of NoC architectures, especially when there are faulty components in the network. In this paper, we present a routing technique that uses an embedded tree for mesh networks to achieve high-performance on-chip communication. In this design, the abundant links not belonging to the embedded tree become shortcuts to reduce the distance for packet routing. We show that our routing is deadlock-free and, with appropriate mapping of the tree, equivalent to the well-known XY routing for mesh networks. Furthermore, when there are faulty components in the network, our switch can still successfully deliver packets through tree re-mapping as long as the network is connected. Our design is evaluated by using static analysis and simulation for faulty networks with various network sizes. The results show that our design achieves superior performance without using a routing table in the switch for faulty mesh on-chip networks.