New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

Author

Shiomi, Toru ; Wada, Tomohisa ; Ohbayashi, Shigeki ; Ohba, Atushi ; Honda, Hiroki ; Ishigaki, Yoshiyuki ; Hatanaka, Masahiro ; Nagao, Shigeo ; Anami, Kenji ; Sumi, Tadashi

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1991

fDate

12-15 May 1991

Abstract

The authors propose a novel bit line architecture, the T-shaped bit line architecture (TSBA), which is suitable for high-speed, high-density and/or large bit-wide configuration SRAMs (static random-access memories). This architecture is applied to 256-kb BiCMOS TTL (transistor-transistor logic) I/O SRAM with a typical access time of 5.8 ns. To achieve sub-6-ns access time, a bipolar Darlington column sense amplifier, a global column decode technique, a shielded data bus technique with TSBA, and 0.8-μm BiCMOS technology are employed

Keywords

BIMOS integrated circuits; SRAM chips; memory architecture; transistor-transistor logic; 0.8 micron; 256 kbit; 5.8 ns; BiCMOS; T-shaped bit line; TSBA; TTL SRAM; access time; bipolar Darlington column sense amplifier; bit line architecture; global column decode technique; shielded data bus; static RAM; static random-access memories; transistor-transistor logic; ultra high speed; BiCMOS integrated circuits; Computer architecture; Decoding; Driver circuits; High performance computing; Large scale integration; Random access memory; Research and development; Standards development; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164124

Filename

164124