Title :
Optimization of collector-substrate capacitance for mixed signal low power BiCMOS
Author :
Sung, J.M. ; Chiu, T.Y. ; Lau, K. ; Liu, T.M. ; Archer, V.D. ; Razavi, B. ; Swartz, R.G. ; Erceg, F.M. ; Ling, M.P. ; Moerschel, K.G. ; Prozonic, M.A. ; Long, T.P.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
This paper reports in detail the process and electrical results of a novel approach to optimize collector-substrate capacitance (C/sub cs/). Shallow arsenic buried layer combined with fully recessed LOCOS isolation have been developed for AT&T´s BEST2 high performance mixed signal BiCMOS. Arsenic lateral autodoping is suppressed by selective epitaxy capping (SEC). A 800 nm fully recessed LOCOS minimizes perimeter component of C/sub cs/ and reduces substrate p-n-p gain. Without invoking expensive trench isolation, n-p-n bipolar device with a conservative 1 /spl mu/m design has sub 10 fF C/sub cs/. Excellent packing density and junction yield are obtained. ECL ring oscillator (A/sub e/=1/spl times/2 /spl mu/m/sup 2/, 500 mV swing) has nominal/minimum delays of 48 ps/37 ps at 0.6 mA/2.1 mA per stage current respectively. BiCMOS phase-locked-loop (emitter width=1 /spl mu/m; gate L/sub eff/=0.7 /spl mu/m) has achieved a world record of 6 GHz operation at 2 V power supply with total power consumption of 60 mW.<>
Keywords :
BiCMOS integrated circuits; arsenic; capacitance; epitaxial growth; integrated circuit technology; ion implantation; mixed analogue-digital integrated circuits; 1 micron; 10 fF; BEST2; Si:As; collector-substrate capacitance; fully recessed LOCOS isolation; mixed-signal low power BiCMOS; selective epitaxy capping; shallow Ar buried layer; BiCMOS integrated circuits; Capacitance; Delay; Doping; Electrical resistance measurement; Epitaxial growth; Etching; Implants; Silicon; Substrates;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324409
