An Analytical Framework with Bounded Deflection Adaptive Routing for Networks-on-Chip

In a Multi-Processor System-on-Chip (MPSoC)-based embedded system with Network-on-chip (NoC) as the communication architecture, routing of the communication traffic among the Processing Elements (PEs) contributes significantly to the overall latency, throughput and energy consumption. Design of an efficient routing algorithm for NoC requires a thorough understanding of the role of individual components of NoC. Simulation based studies are time-consuming and do not provide adequate insight into the design parameters for performance improvement. In this paper, we provide a framework for the analytical study of the NoC components and design an adaptive routing algorithm. Based on the traffic pattern of the communication traffic among PEs, we perform analytical studies based on network calculus and probabilistic analysis. Analytical study relates the design parameters with the worst case and average case latency and buffer requirements. Knowledge obtained from the analytical study is utilized for resource allocation of NoC, which further constitutes the design philosophy of the proposed Bounded Deflection Adaptive Routing (BDAR) algorithm. Our routing algorithm is deadlock-live lock free and efficiently reacts to link congestions. Experimental results based on simulations show that our routing algorithm performs significantly better than some existing static and dynamic routing in terms of link utilization, average and maximum end-to-end latency.