Title :
A 120 MFLOPS CMOS floating-point processor
Author :
Chai, Paul ; Chuk, Ting ; Fong, Yuan Hsin ; Hu, Larry ; Ng, Ken ; Prabhu, Jnyaneshwar ; Quek, Alan ; Samuels, Allen ; Yeun, Joe
Author_Institution :
Weitek Corp., Sunnyvale, CA, USA
Abstract :
A 60-MHz CMOS floating-point processor has been designed with 120 MFLOPS double-precision peak rating and a bus bandwidth of 1.44 GB/s. Using a novel floating-point algorithm, it performs floating-point add, multiply, divide, square-root, and inverses, and it supports parallel 64-bit load and store
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; microprocessor chips; pipeline processing; 1.44 Gbyte/s; 120 MFLOPS; 60 MHz; 64 bit; CMOS; add operations; bus bandwidth; divide operations; double-precision peak rating; floating-point algorithm; floating-point processor; inverses operations; multiply operations; parallel 64-bit load; square root operations; Arithmetic; Bandwidth; CMOS process; Clocks; Delay; Engines; Logic arrays; Pins; Registers; Throughput;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164128
